1. Field of the Invention
This invention relates to circuit testing and, more particularly, to the displaying of test patterns.
2. Description of the Related Art
Circuits are typically tested using an assortment of tests. Tests may be performed on a device by applying external stimuli to a device's inputs under a given set of conditions on a circuit tester and comparing the actual results to a given set of expected results. For example, in FIG. 1, a perspective view diagram of one embodiment of a device tester 10 is shown. Device tester 10 includes a CPU cabinet 100A which is coupled to a device tester component interface 100B via an interface cable 152. Further, device tester 10 includes a user interface 150 coupled to CPU cabinet 100A via an interface cable 151. A device-under-test (DUT) 110 is coupled to device tester component interface 100B using one of a variety of methods and hardware (not shown). The stimuli and the expected results are typically applied to DUT 110 using a test file which is commonly referred to as a test pattern.
Generally, a device test program and the test pattern are loaded into the tester memory (not shown). The test program may include software instructions written in any of a variety of programming languages, including some tester specific languages. The test program is executed by the tester CPU (not shown) and in conjunction with the test pattern a test environment may be created for the DUT. A user may control and monitor the testing process through user interface 150. Further, the user may view and edit the test patterns as well as analyze the test results through user interface 150. In addition, test program and test pattern files may be viewed and edited on a variety of other types of computer systems such as a network workstation or a desktop personal computer, for example.
One type of testing method that is commonly used to test integrated circuits is functional testing. During functional testing, DUT 110 is allowed to operate in one or more of its operating (i.e. functional) modes while the outputs are monitored and compared against a given set of expected results. Depending on the level of complexity of the circuit, functional testing may be an adequate testing method by itself.
However, due to such factors as increased device complexity, gate counts and test pin count constraints it has become more difficult to test a device adequately using only functional testing. In addition, creating large numbers of functional test patterns and then grading those patterns on commercial pattern grading tools can be an exhaustive task that may take many hours of computer time. Further, on many complex circuits, functional test patterns may routinely provide test coverage in the mid 80 percent range, while for many applications test coverage in the mid 90 percent range may be minimally acceptable. Thus another type of testing has become widely used: scan-based testing. Using rigorous design-for-testability techniques and automated test pattern generation (ATPG) tools, scan-based testing has been shown to routinely produce test patterns having test coverage in the upper 90 percent range.
Scan testing typically involves using one or more scan chains. A scan chain is created using scannable elements such as flip-flops that are part of the circuit, although other clocked storage devices may be used. The output of a given flip-flop is coupled to the input of another flip-flop. A large number of flip-flops may be connected in this manner, forming a scan chain that passes through the internal logic of the circuit. The scan chain may be thought of as a serial shift register, in which values are shifted from one register flop to the next. Using this method, multiple scan chains may be formed in a given integrated circuit.
To test a circuit using one type of scan chain, a scan test pattern, which is sometimes referred to as scan data or a test vector, is shifted or clocked into the scan chain using a scan clock in a scan mode, thereby loading each element of the scan chain with a predetermined value. For example, a scan chain containing 50 scan elements will be loaded with 50 predetermined values using 50 scan clock cycles. Following the initial loading, the circuit is then reverted to its normal operating mode. The circuit may then be clocked once with the system clock, allowing the predetermined values to propagate through the individual logic circuits connected to the scan elements. After allowing the circuits a sufficient time to respond, the scan data that is now contained in the scan elements is shifted out of the scan chain using the scan clock in the scan mode. The scan out data is compared with expected results to determine whether the circuit is faulty.
In a typical scan input pattern, logic ones and zeros are clocked into the scan chain. The scan output pattern contains the expected results. The results typically include a logic one, a logic zero or in some cases a “don't care” condition. These logic values are typically represented as different pattern symbols such as ASCII characters. Depending upon the type of tester used, the pattern symbols in the scan input and scan output patterns may be ones and zeros, or the letters ‘H’, ‘L’ and ‘X’ which represent a logic one, a logic zero and a don't care, respectively.
Referring to FIG. 2, an example of a scan pattern is shown. The scan pattern includes a scan input pattern and a scan output pattern. The top portion of the pattern is a scan input pattern and contains 912 scan input values. The bottom portion is a scan output pattern and contains 912 scan output values. The scan input pattern is depicted using ‘H’ and ‘L’ ASCII characters which represent logic values 1 and 0, respectively. The scan output pattern is shown using 1's and 0's which represent logic values 1 and 0, respectively. In addition, the ASCII character ‘M’ is used to represent a “don't care” value. In many cases, the ATPG tool may not be capable of generating an expected value of 1 or zero for a given scan input value. Thus, the ATPG tool may place a “don't care” in the respective location in the scan output pattern.
Many scan chains contain as many as 100,000 flip-flops, and accordingly each scan pattern may have 100,000 corresponding ones and zeros, and 100,000 H, L, and X symbols. Typically, after an ATPG tool generates a test pattern it must be verified for accuracy. In addition, after a device has been tested, failing units may be analyzed to determine the cause of the failure. In either case, a human must view the scan pattern or the results of a device test. The scan patterns may not only be difficult to look at, but it may be difficult to discern information in the context of a complete scan chain.